2 days old

STA/Timing CAD Engineer

Intel
Santa Clara, CA 95050
Job ID: JR0221634
Job Category: Software Engineering
Primary Location: Santa Clara, CA US
Other Locations: US, Arizona, Phoenix;US, California, Folsom;US, Massachusetts, Hudson;US, Oregon, Hillsboro;US, Texas, Austin
Job Type: Experienced Hire

STA/Timing CAD Engineer

Job Description

Responsibilities of the role include, although not limited to:

  • Work closely with design teams to understand and debug Static Timing Analysis tool/flow/methodology issues.

  • Create and maintain flows and scripts to support Static Timing Analysis specific to customer needs.

  • Engage with vendors to drive tool quality improvements and fixes.

  • Drive Static Timing Analysis to improve flows for deep submicron designs.

  • Own regression and testing of design testcases to improve quality of flows deployed to design team.

  • Solid communication and written skills.


Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:
Candidate must have a Bachelor's degree in Electrical/Computer Engineering, Computer Science, or related field with 3+ years experience or Master's degree in Electrical/Computer Engineering, Computer Science, or related field with 1+ years experience in the following:

  • Static Timing Analysis tools/flows/methodology.

  • Programming in TCL.


Preferred Qualifications:

  • Key timing aspects including cross-talk, OCV effects, margins, and constraints.

  • Using and debugging industry standard Static Timing Analysis tools such as Primetime.

  • Design systems.

  • Industry standard Synthesis and Place and Route flows.

  • Experience programming in TCL/Perl/Python.

Inside this Business Group

Product Enablement Solutions Group (PESG) is one of the key pillars, enabling Intel product design teams get to market faster with winning leadership products.



Other Locations

US, Arizona, Phoenix;US, California, Folsom;US, Massachusetts, Hudson;US, Oregon, Hillsboro;US, Texas, Austin


Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.



Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

USExperienced HireJR0221634Santa ClaraProduct Enablement Solutions Group

Categories

Posted: 2022-05-13 Expires: 2022-06-12

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STA/Timing CAD Engineer

Intel
Santa Clara, CA 95050

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