13 days old

Senior Mixed Signal IC Design Engineer - 157666

Xilinx
San Jose, CA 95113
  • Job Code
    157666
Primary Location ' . United States-California-San Jose . '
Job: ' . Design Engineering . '
Schedule: ' . Full-time . '
Description
' . !*!At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

. '

Qualifications
!*!

       5-10 yrs. experience in high speed serial and/or parallel mixed signal PHY/IO designs

       Strong fundamentals and knowledge of mixed signal circuit architecture and design techniques for receiver/transmitter and PLL/DLL/clocking.

       Hand-on design experience in multi-Gbps serial (PCIE, USB, ), parallel high BW memory interface PHY/IOs (DDR4/DDR5, HBM2/HBM3, gDDR5/gDDR6, ) and chip-to-chip links PHY IPs owning

       Experience in mixed signal design circuit blocks such as digital/analog DLLs, duty cycle corrector, clock and data recovery, clock mixer,

       Experience low power design techniques for high speed/custom digital circuit (e.g. CMOS/CML high speed design for counters, dividers, ) design and analysis including transistor level timing sign-off

       Solid understanding of power, area and performance trade-offs in mixed signal IP design

       Design Experience in FinFet advanced CMOS process nodes 16nm/7nm and below coupled with a solid understanding of transistor device performance and fundamentals

       Proficient in AMS design flows, tools, and methodologies. Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools

       Work with project-manager, system architects, IC designers and physical designers  to guarantee quality/timely deliverables meeting projects schedule and technical requirements

       Track record of successfully taking designs to production

       Excellent written and verbal communication skills able to operate without direct supervision but also work cross-functionally, cross-geographies collaborating and being part of a multi-disciplinary team in a dynamic/fast paste environment.

       Exhibit strong initiative and ownership of tasks and responsibilities. Seek help proactively as well as share and pass on knowledge


Job Posting: Aug 6, 2019, 7:16:53 PM

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Posted: 2019-08-07 Expires: 2019-09-16

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Senior Mixed Signal IC Design Engineer - 157666

Xilinx
San Jose, CA 95113

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