1+ months

Senior Design Verification Engineer - 158213

San Jose, CA 95113
  • Job Code
Primary Location ' . United States-California-San Jose . '
Job: ' . Engineering Services . '
Schedule: ' . Full-time . '
' . !*!At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.

Functional Verification and Validation

    • Lead and plan verification of complex digital design blocks by fully understanding the architecture and design specification
    • Interact with architects and design engineers to create a comprehensive verification test plan
    • Design and architect test benches in System Verilog and UVM to complete verification of the design in an efficient manner
    • Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
    • Debug tests with design engineers to deliver functionally correct design blocks
    • Identify and write coverage measures for stimulus quality measurements
    • Perform coverage analysis to identify verification holes and achieve closure on coverage metrics


. '

!*!Education and Experience Requirements
BS with 5 years of experience or MS with 3 years of experience or PhD with a degree in electrical engineering, computer engineering or related equivalent 

Other Qualifications
  • Strong experience in HDL, verification, and general computational logic design/verification concepts

  • Experience in ASIC design flow from frontend to backend is a plus.

  • Proficiency in System Verilog and UVM

  • Prior use of simulation tools/debug environments such as Synopsys VCS, Synopsys VCS-XA, Cadence IES or Mentor Questa is required

  • Proficiency in Perl, Python and/or other scripting language

  • Understanding of DFT, ijtag experience is a plus

  • Understanding of AMBA protocols like AXI4, AXI-STREAM and AHB is a strong plus

  • Basic understanding of formal property checking, gate level simulation, power verification using UPF, reset verification, and/or contention checking is a plus

  • Excellent interpersonal skills, self-motivated

Job Posting: Jan 15, 2020, 7:06:16 PM


Posted: 2020-01-16 Expires: 2020-03-22

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Senior Design Verification Engineer - 158213

San Jose, CA 95113

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