9 days old

Product Development Engineer IO/PLL

Santa Clara, CA 95050
Job ID: JR0127413
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations:
Job Type: Experienced Hire

Product Development Engineer IO/PLL

Job Description

The Data Center Manufacturing Engineering Group is looking for a motivated engineer to join the team to work in the highly challenging environment of product development across Intel's XEON product families!

The product development engineers in this team work on architecture definitions, circuit and logic design and development recommendation for DFT implementations, verification and validation model development, functional and structural test content development with teams worldwide. This team is responsible for:

  • Maintaining Intel's design and manufacturing quality of baseline product to the external world.
  • Ensuring the testability and manufacturability of high speed serial I/O and PLL from architectural design through to production ramp for server CPUs.
  • Ensuring server CPUs' HSIO meeting the electrical parametric specifications before product qualification.

Responsibilities of the role include, although not limited to:

* DFT Design (Design for Test)
* Pre-Silicon validation of Analog test content at IP and full chip level including test writing.
* Test content generation of patterns to support HVM testers as well as Bench DV.
* Silicon debug to identify functional and DFT related bugs and silicon characterization to validate IP.
* Support platform and system level validation teams to identify and close silicon issues.
* Analysis and disposition of early customer returns to drive understanding of design marginalities or develop test content to screen these units where needed.
* Work with Sort and Class teams to deliver high quality analog test content and support improving product health indicators.


You must possess the below minimum qualifications to be initially considered for this position. Experience listed below would be obtained through a combination of your school work/classes/research and/or relevant previous job and/or internship experiences.

Minimum Requirements

- Candidate must possess a Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science or a closely related field plus 3+ years of experience -OR- a Master's Degree in Electrical Engineering, Computer Engineering, Computer Science or a closely related field plus 2+  years of experience with:

  • Test development using automated test equipment (ATE) for high volume manufacturing development.
  • Software programming skills in Perl, Python, C, or C++

Preferred Qualifications

2+ years experience with:

  • IO protocols, system architecture, specs, DFT architectures, and design (PCI Express, 10G KR, QPI, SATA, USB3, etc)
  • Development, evaluation and validation of analog and DFT circuits including concepts such as jitter, margining, squelch, equalization.
  • High volume manufacturing flows and statistical data analysis
  • Driving tester to support debug and characterization of silicon, ability to script experiments for both tester and bench systems.
  • RTL, GLS and VTPsim test writing, simulation and validation
  • Test writing in multiple circuit areas in System Verilog, Python, or similar language.
  • Silicon debug and characterization of new products including working with platform and system level validation teams to identify and close silicon issues.
  • Using oscilloscopes, J-bert, VNA, pattern generator, source meter, spectrum and Logic analyzer.
  • Understanding of circuits and logic design methodology.
  • Understanding of device physics.
Inside this Business Group

The Infrastructure and Platform Solutions Group (IPSG) builds the silicon and platform infrastructure for Intel's silicon design teams. IPSG is comprised of a reusable pool of infrastructure IP blocks, design enabling services such as tools and automation, and a best-in-class post silicon ecosystem that ramps quickly to high volume manufacturing and validation. Our primary mission is to protect Intel's brand by providing the infrastructure necessary to enable all of Intel's products to hit the market on a dependable and predictable cadence.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....

USExperienced HireJR0127413Santa Clara


Posted: 2020-02-07 Expires: 2020-03-09

Before you go...

Our free job seeker tools include alerts for new jobs, saving your favorites, optimized job matching, and more! Just enter your email below.

Share this job:

Product Development Engineer IO/PLL

Santa Clara, CA 95050

Join us to start saving your Favorite Jobs!

Sign In Create Account
Powered ByCareerCast