1+ months

Principal Engineer, Pre-si Verification

Intel
Santa Clara, CA 95050
Job ID: JR0140014
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations: US, Oregon, Hillsboro
Job Type: Experienced Hire

Principal Engineer, Pre-si Verification

Job Description

About the Business Group:

IP Engineering Group builds IPs that power Intel's leadership products and power our customer's silicon.

Responsibilities:

The candidate will be part of the IP design team chartered with delivering IP multiple server SOCs across Intel.  This is Principal Engineer role, which is a hands-on, highly technical individual contributor role.
 

Candidate responsibilities include the following:

  • Define and enhance methodologies for pre-silicon validation of high complexity IP improving the overall efficiency and velocity of the pre-silicon validation team.
  • Interact closely with the architecture and design teams, influencing product definition, implementation and validation.
  • Create, define and develop system validation environment and test suites
  • Responsible for the development of methodologies, execution of validation test plans, test sequences and directed tests.
  • Mentor and guide junior verification engineers
     

The role requires the following attributes in the candidate:
 

  • Proven track record in ASIC verification from environment development to tests development
  • Hands-on verification experience and high-proficiency using SystemVerilog and OVM/UVM2
  • Proven track record of developing complex verification collaterals quickly and solid simulation debug skills.
  • In-depth understanding of computer architecture, PCI-Express or other I/O protocols, and any coherency protocols
     


Qualifications

Experience Required:                                                       

  • Education: BS/MS in Electrical or Computer Engineering or related technical discipline
  • 12+ years of experience as a Pre-Si Validation designer including experience in:
    • ASIC verification from environment development to tests development
    • Hands-on verification experience using SystemVerilog and OVM/UVM2
    • In-depth understanding of computer architecture, PCI-Express or other I/O protocols, and any coherency protocols
    • C/C++ and Scripting experience

Additional Preferred Experience:                                 

  • x86 knowledge is preferred but not required
  • prior experience role modeling and mentoring junior engineers
  • strong communication skills to influence partners and stakeholders
  • change agent mindset
Inside this Business Group

The Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.



Other Locations

US, Oregon, Hillsboro



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance....



Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter....

USExperienced HireJR0140014Santa Clara

Categories

Posted: 2020-07-30 Expires: 2020-09-27

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Principal Engineer, Pre-si Verification

Intel
Santa Clara, CA 95050

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