1+ months

GPE Datacenter - Datacenter PCB Layout Design engineer

台北市, TPE 110
Job ID: JR0159799
Job Category: Engineering
Primary Location: Taipei, TPE TW
Other Locations:
Job Type:

GPE Datacenter - Datacenter PCB Layout Design engineer

Job Description

Intel desires entry into market segments served by high-performance discrete graphics. Participation in market segments served by discrete graphics requires the delivery of reference platforms to downstream customers with sufficient confidence in the design to ramp this design or very close derivative into high volume production quickly. Intel is building this capability and now seeks to create a discrete graphics Platform System Engineering team in Taiwan.  Are you interested?  Then GPE has an opportunity for you.  

In GPE, we are responsible for delivering leading GPU solutions to integrated and discrete graphics in data center and will continue to deliver a pipeline of innovation supporting the complete Intel platform, including CPU, memory, and accelerators! We are looking for a PCB Layout Design engineer to join our team.

Key Responsibilities

The PCB Design Engineer, will drive the technical development, on time delivery and cost optimization of PCB solutions for products based on Intel's discrete graphics chips. In this role you will design, in collaboration with engineers from all competencies of the System Engineering team (thermal, mechanical, board design, power design, SI/PI etc.), PCB solutions for pcie graphics cards, OAMs and create product reference designs, and/or graphics systems. You will drive all aspects of the PCB design, from scoping/planning, pathfinding and trial layout, material selection, vendor engagement, layout review and more for all new designs. You will work closely with internal Intel DFM team to ensure design is compliance with Intel’s DFA and DFM practices. You will generate PCB output files to be sent for Design for Manufacturing (DFM) review and board houses for fabrication. In addition, you may work with key OEM/ODM/ODC partners in support of their designs.

Required Background

This is a critical position within the Intel GPE development organization. The successful candidate will have demonstrated a successful track record of delivering high quality designs on time, working and influencing industry leaders, and engaging with OEMs and partners. The market segments served by discrete graphics are fast moving, therefore the successful candidate shall demonstrate a high level of comfort with change and change management.


Required Experience

  • 10+ years of experience delivering high-speed interfaces (25Gbps+ in differential and 10Gbps+ in single ended) and high power multi-layer PCB
  • Excellent working knowledge of PCB Design within Cadence Allegro PCB Design
  • Excellent knowledge of power delivery, thermal, mechanical, electrical and SI, PI design principles
  • Proficient with Constraint Manager
  • Familiar with SKILL, LISP, PERL code for scripting
  • Experience in delivering products to market for successful high-volume production
  • Knowledge of DFM, DFA, DFC
  • Experience with manufacturing processes and implications to yield
  • Knowledge of finishing options and associated costs
  • Experience with cost optimization
  • Ability to drive manufacturers remotely to resolve technical issues or push for timely delivery
  • Experience with the typical requirements of regulatory and compliance validation for consumer electronics
Inside this Business Group

Intel Architecture, Graphics, and Software (IAGS) brings Intel's technical strategy to life. We have embraced the new reality of competing at a product and solution level—not just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve what's never been done before. We've also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.



Posted: 2021-02-26 Expires: 2021-05-15

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GPE Datacenter - Datacenter PCB Layout Design engineer

台北市, TPE 110

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