1+ months

DFD Validation Lead/Engineer

Intel
Santa Clara, CA 95050
Job ID: JR0163052
Job Category: Engineering
Primary Location: Santa Clara, CA US
Other Locations: US, Oregon, Hillsboro
Job Type: Experienced Hire

DFD Validation Lead/Engineer

Job Description

Come join Intel's Xeon Silicon Design Group as a DFD Validation Engineer for both simulation and emulation platforms working on exciting products fueling the data center growth. As a member of SOC Val Team, you will work with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites.

Your responsibilities will include but not be limited to:

  • Validation of DFD features in sub-system and SOC Validation environments
  • Participate in development of verification/validation environment of complex design components
  • Participate to determine architecture for validation for chip and system level validation
  • Defines module interfaces/formats for simulation.
  • Develop and build test benches for design under test. Identify, document and execute test plans on emulation platforms, develop and debug random constrain verification test suite to fully verify the design under test
  • Participate in definition of verification/validation infrastructure, and documentation for IP, SoC System on a Chip and system level development
  • Experience with pre-silicon validation of designs which include processor cores and custom logic working together.

The ideal candidate should exhibit the following behavioral traits:

  • Strong independence and proven ability to set and meet own goals
  • Strong problem-solving skills and ability to multitask
  • Excellent written and verbal communication skills
  • Ability to work in a dynamic and team-oriented environment


Qualifications

Must have a bachelor's degree in Electrical/Computer Engineering, Computer Science or related field plus 4+ years of relevant experience. OR a master's degree in Electrical/Computer Engineering, Computer Science or related field with 3+ years of relevant experience:

Your experience should be in the following:

  • Validation experience on DFD
  • Experience with reading and interpreting technical specs and Register Transfer Level (RTL) code
  • Experience with Computer Architecture or pre-Si verification.
  • Experience with Logic Design verification
  • Experience with Microprocessor or Chipset design methods
  • Experience with pre-Silicon simulation tool flows required.
  • Example tools include but not limited to:- Synopsys VCS, Verdi and DVE
  • Knowledge of UVM, SystemVerilog developing verification test benches and constrained random validation
  • Experience with modern CPU architecture, such as memory cache hierarchy, scheduler, pipeline
Inside this Business Group

Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap.



Other Locations

US, Oregon, Hillsboro



Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

USExperienced HireJR0163052Santa Clara

Categories

Posted: 2021-03-29 Expires: 2021-05-27

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DFD Validation Lead/Engineer

Intel
Santa Clara, CA 95050

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