1+ months

Design Engineer (Verification Contract) - 158044

Singapore, Singapore
  • Job Code
Primary Location ' . Singapore-Singapore-Singapore . '
Job: ' . Design Engineering . '
Schedule: ' . Full-time . '
' . !*!

At Xilinx, we are leading the industry transformation to build an adaptable, intelligent world. ARE YOU bold, collaborative, and creative? At Xilinx, we hire and develop leaders and innovators who want to revolutionize the world of technology. We believe that by embracing diverse ideas, pushing boundaries, and working together as ONEXILINX, anything is possible.

Our culture of innovation began with the invention of the Field Programmable Gate Array (FPGA), and with the 2018 introduction of our Adaptive Compute Acceleration Platform (ACAP), has made a quantum leap in capability, solidifying our role as the adaptable platform supplier of choice. From the start, we have always believed in providing inventors with products and platforms that are infinitely adaptable. From self-driving cars, to world-record genome processing, to AI and big data, to the world's first 5G networks, we empower the world's builders and visionaries whose ideas solve every day problems and enhance people's lives.

If you are PASSIONATE, ADAPTABLE, and INNOVATIVE, Xilinx is the right place for you! At Xilinx we care deeply about creating meaningful development experiences while building a strong sense of belonging and connection. We foster an environment of empowered learning, wellness, community engagement, and recognition, so you can focus on work that matters - world class technology that improves the way we live and work. We are ONEXILINX.


Job Description


This is an IC Design Verification Engineer position in the Wired and Wireless Group on a contract basis to perform the following key activities

  • Develop and Review Test Plan based on design specification
  • Develop constrained-Random verification environment for complex DUT
  • Implement coverage matrix using cover point and assertion
  • Create and debug tests for DUT
  • Resolve bugs with remote designers



. '



  • 5 years of hands on experience with SystemVerilog/UVM
  • Bachelor/Masters Degree in Electrical/Electronics/Computer Engineering
  • Strong understanding of verification process from test plan to coverage completion
  • Strong communication and Analytical skills
  • Understanding of HDL (Verilog, VHDL)
  • Experience with designing with FPGA using Vivado is a plus

Job Posting: Oct 23, 2019, 8:04:31 PM


Posted: 2019-10-24 Expires: 2020-07-26

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Design Engineer (Verification Contract) - 158044

Singapore, Singapore

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