1+ months

DDR Design Verification Senior Staff Engineer

Qualcomm
Job Id E1980006
Job Title DDR Design Verification Senior Staff Engineer
Post Date 01/29/2020
Company Qualcomm Technologies, Inc.
Job Area Engineering - Hardware
Location India - Bangalore
Job Overview Candidate will be responsible for leading RTL IP/Subsystem verification of DDR (controller + PHY) block, which form an integral part of the complex Snapdragon series of Qualcomm SOCs. He/She will be responsible for managing the activities spanning verification plan definition, DV environment development in SV/UVM, SV/C based test case development, Design verification at RTL level, DV Coverage analysis, Coverage improvement at block and SOC level. The role requires actively interfacing with wider teams dealing at SoC, Post-Silicon qualification to close end-to-end requirements & ensure seamless drivers deployment.
Minimum Qualifications 12+ years of experience in IP level verification targeting development of System Verilog-UVM based test benches.
Expertise in verifying complex designs from system as well as block level, through design flow.
Exposure to LPDDR3, LPDDR4, LPDDR5, DDR3, DDR4, DDR5 protocols & related controller/PHY designs stands highly desirable.
Working knowledge of DFI, AMBA, AXI fully required.
Experience with MODELSIM/VCS/SILOTI is required.


Preferred Qualifications 12+ years of experience in IP level verification targeting development of System Verilog-UVM based test benches. Expertise in verifying complex designs from system as well as block level, through design flow. Exposure to LPDDR3, LPDDR4, LPDDR5, DDR3, DDR4, DDR5 protocols & related controller/PHY designs stands highly desirable. Working knowledge of DFI, AMBA, AXI fully required. Experience with MODELSIM/VCS/SILOTI is required.
Education Requirements Required: Bachelor's/ Masters - Computer Engineering and/or Computer Science and/or Electrical Engineering
*LI-IND
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Posted: 2020-01-15 Expires: 2020-02-28

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DDR Design Verification Senior Staff Engineer

Qualcomm

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